Burr-Brown INA125 pdf datasheet download

INSTRUMENTATION AMPLIFIER With Precision Voltage Reference

FEATURES
l LOW QUIESCENT CURRENT: 460mA
l PRECISION VOLTAGE REFERENCE:
1.24V, 2.5V, 5V or 10V
l SLEEP MODE
l LOW OFFSET VOLTAGE: 250mV max
l LOW OFFSET DRIFT: 2mV/°C max
l LOW INPUT BIAS CURRENT: 20nA max
l HIGH CMR: 100dB min
l LOW NOISE: 38nV/ÖHz at f = 1kHz
l INPUT PROTECTION TO ±40V
l WIDE SUPPLY RANGE
Single Supply: 2.7V to 36V
Dual Supply: ±1.35V to ±18V
l 16-PIN DIP AND SO-16 SOIC PACKAGES

APPLICATIONS
l PRESSURE AND TEMPERATURE BRIDGE
AMPLIFIERS
l INDUSTRIAL PROCESS CONTROL
l FACTORY AUTOMATION
l MULTI-CHANNEL DATA ACQUISITION
l BATTERY OPERATED SYSTEMS
l GENERAL PURPOSE INSTRUMENTATION

DESCRIPTION
The INA125 is a low power, high accuracy instrumentation
amplifier with a precision voltage reference. It
provides complete bridge excitation and precision differential-
input amplification on a single integrated
circuit.
A single external resistor sets any gain from 4 to
10,000. The INA125 is laser-trimmed for low offset
voltage (250mV), low offset drift (2mV/°C), and high
common-mode rejection (100dB at G = 100). It operates
on single (+2.7V to +36V) or dual (±1.35V to
±18V) supplies.
The voltage reference is externally adjustable with pinselectable
voltages of 2.5V, 5V, or 10V, allowing use
with a variety of transducers. The reference voltage is
accurate to ±0.5% (max) with ±35ppm/°C drift (max).
Sleep mode allows shutdown and duty cycle operation
to save power.
The INA125 is available in 16-pin plastic DIP and
SO-16 surface-mount packages and is specified for
the –40°C to +85°C industrial temperature range.


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Texas Instruments CC1100 pdf datasheet download

CC1100
Low-Power Sub- 1 GHz RF Transceiver

Applications
• Ultra low-power wireless applications
operating in the 315/433/868/915 MHz
ISM/SRD bands
• Wireless alarm and security systems
• Industrial monitoring and control
• Wireless sensor networks
• AMR – Automatic Meter Reading
• Home and building automation

Product Description
The CC1100 is a low-cost sub- 1 GHz
transceiver designed for very low-power
wireless applications. The circuit is mainly
intended for the ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency bands at 315, 433, 868, and 915
MHz, but can easily be programmed for
operation at other frequencies in the 300-348
MHz, 400-464 MHz and 800-928 MHz bands.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data up to 500 kBaud.
CC1100 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.

The main operating parameters and the 64-
byte transmit/receive FIFOs of CC1100 can be
controlled via an SPI interface. In a typical
system, the CC1100 will be used together with a
microcontroller and a few additional passive
components.

Key Features
RF Performance
• High sensitivity (–111 dBm at 1.2 kBaud,
868 MHz, 1% packet error rate)
• Low current consumption (14.4 mA in RX,
1.2 kBaud, 868 MHz)
• Programmable output power up to +10
dBm for all supported frequencies
• Excellent receiver selectivity and blocking
performance
• Programmable data rate from 1.2 to 500
kBaud
• Frequency bands: 300-348 MHz, 400-464
MHz and 800-928 MHz
Analog Features
• 2-FSK, GFSK, and MSK supported as
well as OOK and flexible ASK shaping
• Suitable for frequency hopping systems
due to a fast settling frequency
synthesizer: 90us settling time
• Automatic Frequency Compensation
(AFC) can be used to align the frequency
synthesizer to the received centre
frequency
• Integrated analog temperature sensor
Digital Features
• Flexible support for packet oriented
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
• Efficient SPI interface: All registers can be
programmed with one “burst” transfer
• Digital RSSI output
• Programmable channel filter bandwidth
• Programmable Carrier Sense (CS)
indicator
• Programmable Preamble Quality Indicator
(PQI) for improved protection against
false sync word detection in random noise
• Support for automatic Clear Channel
Assessment (CCA) before transmitting
(for listen-before-talk systems)
• Support for per-package Link Quality
Indication (LQI)
• Optional automatic whitening and dewhitening
of data
Low-Power Features
• 400nA SLEEP mode current consumption
• Fast startup time: 240us from sleep to RX
or TX mode (measured on EM reference
design [5] and [6])
• Wake-on-radio functionality for automatic
low-power RX polling
• Separate 64-byte RX and TX data FIFOs
(enables burst mode data transmission)
General
• Few external components: Completely onchip
frequency synthesizer, no external
filters or RF switch needed
• Green package: RoHS compliant and no
antimony or bromine
• Small size (QLP 4x4 mm package, 20
pins)
• Suited for systems targeting compliance
with EN 300 220 (Europe) and FCC CFR
Part 15 (US).
• Support for asynchronous and
synchronous serial receive/transmit mode
for backwards compatibility with existing
radio communication protocols

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MSP430x1xx Family User's Guide pdf datasheet download

MSP430x1xx Family User's Guide

About This Manual
This manual discusses modules and peripherals of the MSP430x1xx family of
devices. Each discussion presents the module or peripheral in a general
sense. Not all features and functions of all modules or peripherals are present
on all devices. In addition, modules or peripherals may differ in their exact
implementation between device families, or may not be fully implemented on
an individual device or device family.
Pin functions, internal signal connections and operational paramenters differ
from device-to-device. The user should consult the device-specific datasheet
for these details.
Related Documentation From Texas Instruments
For related documentation see the web site http://www.ti.com/msp430.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates,
uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Notational Conventions
Program examples, are shown in a special typeface.

1.1 Architecture

The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock
system that interconnect using a von-Neumann common memory address
bus (MAB) and memory data bus (MDB). Partnering a modern CPU with
modular memory-mapped analog and digital peripherals, the MSP430 offers
solutions for demanding mixed-signal applications.
Key features of the MSP430x1xx family include:
Ultralow-power architecture extends battery life
0.1-μA RAM retention
0.8-μA real-time clock mode
250-μA / MIPS active
High-performance analog ideal for precision measurement
12-bit or 10-bit ADC — 200 ksps, temperature sensor, VRef
12-bit dual-DAC
Comparator-gated timers for measuring resistive elements
Supply voltage supervisor
16-bit RISC CPU enables new applications at a fraction of the code size.
Large register file eliminates working file bottleneck
Compact core design reduces power consumption and cost
Optimized for modern high-level programming
Only 27 core instructions and seven addressing modes
Extensive vectored-interrupt capability
In-system programmable Flash permits flexible code changes, field
upgrades and data logging

1.2 Flexible Clock System

The clock system is designed specifically for battery-powered applications. A
low-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHz
watch crystal. The ACLK can be used for a background real-time clock self
wake-up function. An integrated high-speed digitally controlled oscillator
(DCO) can source the master clock (MCLK) used by the CPU and high-speed
peripherals. By design, the DCO is active and stable in less than 6 μs.
MSP430-based solutions effectively use the high-performance 16-bit RISC
CPU in very short bursts.
Low-frequency auxiliary clock = Ultralow-power stand-by mode
High-speed master clock = High performance signal processing


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Texas Instruments TL494 pdf datasheet download

Texas Instruments TL494

FEATURES

DESCRIPTION

PULSE-WIDTH-MODULATION CONTROL CIRCUITS

· Complete PWM Power-Control Circuitry
· Uncommitted Outputs for 200-mA Sink or
Source Current
· Output Control Selects Single-Ended or
Push-Pull Operation
· Internal Circuitry Prohibits Double Pulse at
Either Output
· Variable Dead Time Provides Control Over
Total Range
· Internal Regulator Provides a Stable 5-V
Reference Supply With 5% Tolerance
· Circuit Architecture Allows Easy

Synchronization
The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.
The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator,
a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from –0.3 V to VCC – 2 V. The dead-time control
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the output-control
function. The architecture of this device prohibits the possibility of either output being pulsed twice during
push-pull operation.
The TL494C is characterized for operation from 0°C to 70°C. The TL494I is characterized for operation from
–40°C to 85°C.

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Texas Instruments MAX232 pdf datasheet download

MAX232

Meets or Exceeds TIA/EIA-232-F and ITU
Recommendation V.28
Operates From a Single 5-V Power Supply
With 1.0- F Charge-Pump Capacitors
Operates Up To 120 kbit/s
Two Drivers and Two Receivers
±30-V Input Levels
Low Supply Current . . . 8 mA Typical
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
Upgrade With Improved ESD (15-kV HBM)
and 0.1- F Charge-Pump Capacitors is
Available With the MAX202
Applications
− TIA/EIA-232-F, Battery-Powered Systems,
Terminals, Modems, and Computers
description/ordering information

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F
voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels.

These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs.

Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments LinASIC library.

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

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Texas Instruments CD4060B pdf datasheet download

CD4060B consists of an oscillator
section and 14 ripple-carry binary counter
stages. The oscillator configuration allows
design of either RC or crystal oscillator
circuits.

A RESET input is provided which
resets the counter to the all-O’s state and
disables the oscillator. A high level on the
RESET line accomplishes the reset function.
All counter stages are master-slave flip-flops.
The state of the counter is advanced one step
in binary order on the negative transition of I
(and O).

All inputs and outputs are fully
buffered. Schmitt trigger action on the
input-pulse line permits unlimited
input-pulse rise and fall times.
The CD4060B-series types are supplied in
16-lead hermetic dual-in-line ceramic packages
(F3A suffix), 16-lead dual-in-line plastic
packages (E suffix), 16-lead small-outline
packages (M, M96, MT, and NSR suffixes), and
16-lead thin shrink small-outline packages (PW
and PWR suffixes).


Click here to download Texas Instruments CD4060B pdf datasheet


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MACRONIX MX29LV320DBT flash pdf datasheet download

MX29LV320D T/B

32M-BIT [4M x 8 / 2M x 16] 3V SUPPLY FLASH MEMORY

FEATURES
GENERAL FEATURES
• Byte/Word switchable
- 4,194,304 x 8 / 2,097,152 x 16
• Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
• Extra 64K-Byte sector for security
- Features factory locked and identifiable, and customer lockable
• Twenty-Four Sector Groups
- Provides sector group protect function to prevent program or erase operation in the protected sector group
- Provides chip unprotect function to allow code changing
- Provides temporary sector group unprotect function for code changing in previously protected sector groups
• Power Supply Operation
- Vcc 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to 1.5 x Vcc
• Low Vcc write inhibit : Vcc ≤ Vlko
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Functional compatible with MX29LV320C T/B device
PERFORMANCE
• High Performance
- Fast access time: 70ns
- Fast program time: 11us/word typical utilizing accelerate function
- Fast erase time: 0.7s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• Typical 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Provides accelerated program capability


Click here to download MACRONIX MX29LV320DBT flash pdf datasheet


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