Monday, September 24, 2012
TS5A3357 Texas Instruments TI pdf datasheet download
TS5A3357
SINGLE 5-Ω SP3T ANALOG SWITCH
5-V/3.3-V 3:1 MULTIPLEXER/DEMULTIPLEXER
FEATURES
· Specified Break-Before-Make Switching
· Low ON-State Resistance
· High Bandwidth
· Control Inputs Are 5.5-V Tolerant
· Low Charge Injection
· Excellent ON-State Resistance Matching
· Low Total Harmonic Distortion (THD)
· 1.65-V to 5.5-V Single-Supply Operation
· Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
· ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Click here to download TS5A3357 Texas Instruments TI pdf datasheet
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tms320c6713 Texas Instruments TI pdf datasheet download
tms320c6713.pdf
Highest-Performance Floating-Point Digital
Signal Processor (DSP)
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 225-, 200-MHz (GDP), and 200-, 167-MHz
(PYP) Clock Rates
− 4.4-, 5-, 6-Instruction Cycle Times
− 1800/1350, 1600/1200, and 1336/1000
MIPS/MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available
Advanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− Two ALUs (Fixed-Point)
− Four ALUs (Floating- and Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
L1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two McASPs
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Up to 16 transmit pins
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I2C Bus)
Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
208-Pin PowerPAD Plastic (Low-Profile)
Quad Flatpack (PYP)
272-BGA Packages (GDP)
0.13-μm/6-Level Copper Metal Process
− CMOS Technology
3.3-V I/Os, 1.2-V‡ Internal (GDP & PYP)
Click here to download tms320c6713 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Highest-Performance Floating-Point Digital
Signal Processor (DSP)
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 225-, 200-MHz (GDP), and 200-, 167-MHz
(PYP) Clock Rates
− 4.4-, 5-, 6-Instruction Cycle Times
− 1800/1350, 1600/1200, and 1336/1000
MIPS/MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available
Advanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− Two ALUs (Fixed-Point)
− Four ALUs (Floating- and Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
L1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two McASPs
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Up to 16 transmit pins
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I2C Bus)
Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
208-Pin PowerPAD Plastic (Low-Profile)
Quad Flatpack (PYP)
272-BGA Packages (GDP)
0.13-μm/6-Level Copper Metal Process
− CMOS Technology
3.3-V I/Os, 1.2-V‡ Internal (GDP & PYP)
Click here to download tms320c6713 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
tlv274 Texas Instruments TI pdf datasheet download
tlv274.pdf
Rail-To-Rail Output
Wide Bandwidth . . . 3 MHz
High Slew Rate . . . 2 .4 V/μs
Supply Voltage Range . . . 2.7 V to 16 V
Supply Current . . . 550 μA/Channel
Input Noise Voltage . . . 39 nV/√Hz
Input Bias Current . . . 1 pA
Specified Temperature Range
0°C to 70°C . . . Commercial Grade
−40°C to 125°C . . . Industrial Grade
Ultrasmall Packaging
− 5 Pin SOT-23 (TLV271)
− 8 Pin MSOP (TLV272)
Ideal Upgrade for TLC27x Family
description
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended industrial
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz
bandwidth from only 550 μA.
Like the TLC27x, the TLV27x is fully specified for 5-V and ±5-V supplies. The maximum recommended supply
voltage is 16 V, which allows the devices to be operated from a variety of rechargeable cells (±8 V supplies down
to ±1.35 V).
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an attractive alternative for the TLC27x in battery-powered applications.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range
of many micropower microcontrollers available today including TI’s MSP430.
Click here to download tlv274 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Rail-To-Rail Output
Wide Bandwidth . . . 3 MHz
High Slew Rate . . . 2 .4 V/μs
Supply Voltage Range . . . 2.7 V to 16 V
Supply Current . . . 550 μA/Channel
Input Noise Voltage . . . 39 nV/√Hz
Input Bias Current . . . 1 pA
Specified Temperature Range
0°C to 70°C . . . Commercial Grade
−40°C to 125°C . . . Industrial Grade
Ultrasmall Packaging
− 5 Pin SOT-23 (TLV271)
− 8 Pin MSOP (TLV272)
Ideal Upgrade for TLC27x Family
description
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended industrial
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz
bandwidth from only 550 μA.
Like the TLC27x, the TLV27x is fully specified for 5-V and ±5-V supplies. The maximum recommended supply
voltage is 16 V, which allows the devices to be operated from a variety of rechargeable cells (±8 V supplies down
to ±1.35 V).
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an attractive alternative for the TLC27x in battery-powered applications.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range
of many micropower microcontrollers available today including TI’s MSP430.
Click here to download tlv274 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
tlc27l2a Texas Instruments TI pdf datasheet download
tlc27l2a.pdf
Trimmed Offset Voltage:
TLC27L7 . . . 500 μV Max at 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 μV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
Ultra-Low Power . . . Typically 95 μW
at 25°C, VDD = 5 V
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up immunity
description
The TLC27L2 and TLC27L7 dual operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, extremely low power, and high
gain.
These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage
stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and low power consumption make these cost-effective
devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available
(C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7
(500 μV). These advantages, in combination with good common-mode rejection and supply voltage rejection,
make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and
TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption,
making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input
voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-Suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
Click here to download tlc27l2a Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Trimmed Offset Voltage:
TLC27L7 . . . 500 μV Max at 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 μV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
Ultra-Low Power . . . Typically 95 μW
at 25°C, VDD = 5 V
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up immunity
description
The TLC27L2 and TLC27L7 dual operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, extremely low power, and high
gain.
These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage
stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and low power consumption make these cost-effective
devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available
(C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7
(500 μV). These advantages, in combination with good common-mode rejection and supply voltage rejection,
make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and
TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption,
making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input
voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-Suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
Click here to download tlc27l2a Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
TAS1020B Texas Instruments TI pdf datasheet download
TAS1020B
USB Streaming Controller
1.2 Description
The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed
specifically for applications that require isochronous data streaming. Applications include digital speakers,
which require the streaming of digital audio data between the host PC and the speaker system via the
USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the
USB Audio Class 1.0 Specification.
The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU
memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization,
the boot loader program downloads the application program code to a 6,016-byte RAM from either the
host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control,
interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint
transactions.
The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In
addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT
endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint
configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.
The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support
several industry standard serial interface protocols. These protocols include the audio codec (AC) '97
Revision 1.X, the AC '97 Revision 2.X and several inter-IC sound (I2S) modes.
A direct memory access (DMA) controller with two channels is provided for streaming the USB
isochronous data packets to/from the codec port interface. Each DMA channel can support one USB
isochronous endpoint.
An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB
synchronization modes, which include asynchronous, synchronous and adaptive.
Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit
general-purpose input/output (GPIO) ports.
The TAS1020B device is implemented in a 3.3-V 0.25 μm CMOS technology.
Click here to download TAS1020B Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
USB Streaming Controller
1.2 Description
The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed
specifically for applications that require isochronous data streaming. Applications include digital speakers,
which require the streaming of digital audio data between the host PC and the speaker system via the
USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the
USB Audio Class 1.0 Specification.
The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU
memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization,
the boot loader program downloads the application program code to a 6,016-byte RAM from either the
host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control,
interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint
transactions.
The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In
addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT
endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint
configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.
The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support
several industry standard serial interface protocols. These protocols include the audio codec (AC) '97
Revision 1.X, the AC '97 Revision 2.X and several inter-IC sound (I2S) modes.
A direct memory access (DMA) controller with two channels is provided for streaming the USB
isochronous data packets to/from the codec port interface. Each DMA channel can support one USB
isochronous endpoint.
An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB
synchronization modes, which include asynchronous, synchronous and adaptive.
Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit
general-purpose input/output (GPIO) ports.
The TAS1020B device is implemented in a 3.3-V 0.25 μm CMOS technology.
Click here to download TAS1020B Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
SN74LVC4245A Texas Instruments TI pdf datasheet download
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
FEATURES
Bidirectional Voltage Translator
· 5.5 V on A Port and 2.7 V to 3.6 V on B Port
· Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
<br/>
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device
without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to
align with the conventional '245 pinout.
Click here to download SN74LVC4245A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
FEATURES
Bidirectional Voltage Translator
· 5.5 V on A Port and 2.7 V to 3.6 V on B Port
· Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
<br/>
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device
without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to
align with the conventional '245 pinout.
Click here to download SN74LVC4245A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet download
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QA
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
Click here to download SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QA
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
Click here to download SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
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