sn74lvc1g00.pdf
| FEATURES | |
| ?Available in the Texas Instruments NanoStar? | ?Ioff Supports Partial-Power-Down Mode |
| Package | Operation |
| ?Supports 5-V VCC Operation | ?Latch-Up Performance Exceeds 100 mA Per |
| ?Inputs Accept Voltages to 5.5 V | JESD 78, Class II |
| ?Max tpd of 3.8 ns at 3.3 V | ?ESD Protection Exceeds JESD 22 |
| ?Low Power Consumption, 10-霢 Max ICC | ?2000-V Human-Body Model (A114-A) |
| ??4-mA Output Drive at 3.3 V | ?1000-V Charged-Device Model (C101) |
DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
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DatasheetDoc-Texas Instruments TI pdf datasheet download
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